FANUC Alarm PRIO-020 — STOP I/O Link comm error %x, %x, %x, %x (hex)

Description

Indicates that an error has been detected in communication between the MAIN CPU PCB and the process I/O board, Model-A I/O racks, or Model-B I/O interface units. The most common s of this are the following: o Power to a remote I/O rack or Model-B I/O interface unit is interrupted. o The cable between the MAIN CPU PCB and the process I/O board, racks, or Model-B interface units has been disconnected or is faulty . o Electrical interference between the I/O cables and other cables. This can be eliminated by physically separating the I/O cables from other wiring. In very electrically noisy environments, it might be necessary to use optical isolators with these cables.

Remedy · Remède

Check the cabling between theMAIN CPU PCB (JB-18 connector) and the process I/O board and/or model A or B interface modules. Check power to the remote Model A I/O racks and model B I/O interface modules. If corrections to these do not correct the problem, check the four numbers displayed in this error message. The first value must be interpreted bit-wise. If a bit is 1, the corresponding condition has been detected: Bit 0: (CFER) A CRC or framing error has been detected by the SLC-2 chip on the MAIN CPU PBC. This is most frequently the result of the problems listed above. Otherwise, it might indicate faulty SLC-2 chip, wiring between this and the JB-1B connector on the main PCB, or faulty process I/O, model-A I/O rack, or model-B interface unit. Bit 1: (CALM) An error has been detected by a slave SLC-2 (process I/O board, Model-A rack, or Model B interface unit). More information is provided by the second number displayed with the PRIO-020 error. Bit 2: (CMER) A communication error has been detected by a slave SLC2. The potential s are similar to those for a CFER. Bit 3: (IPRER): Internal parity error accessing SLC-2 internal RAM. This indicates a faulty SLC-2 chip. In this case, the third and fourth numbers displayed with the PRIO-020 error is the address and and data for which the error was detected. This indicates a faulty SLC-2 chip. Bit 4: (OPRER): Parity error accessing external RAM by the SLC-2 chip. This might indicate bad DRAM or CMOS memory on the MAIN CPU PCB. Bit 5: (ALMI): Indicates an alarm signalled from outside the SLC-2. Check the controller Alarm Log for other errors reported. Bit 6: (BSY): Auto scan is running. This might be either 0 or 1 and does not indicate an error. Bit 7: (CEND): Auto-scan cycle has completed. This might be either 0 or 1 and does not indicate an error. The second number displayed is significant only if the CMER bit above is one. Bits 0-4: Indicate the position in the I/O Link chain of the slave unit in which error was detected. A value of 1 indicates the unit connected directly to the I/O LINK connector. Bit 5 (CFER): Indicates a CRC or framing error detected by the slave SLC-2. The s are similar to those for a CFER error detected by the MAIN CPU SLC-2. Bit 6 (ALMI): Indicates an error asserted outside the slave SLC-2. This may indicate a problem with process I/O board, model-B I/O rack, or model-B interface unit hardware. Bit 7 (SYALM): Indicates a watchdog alarm or parity error detected by the slave SLC-2. This may indicate a problem with the process I/O board, model-A rack, or model-B interface unit.

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